The present invention relates to an apparatus and a method for writing an address conversion table. Particularly, the present invention relates to an apparatus and a method for writing, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory.
A non-volatile memory, such as a flash memory and a phase-change memory, has a limitation in the number of rewrites of data. As a result, the data cannot be rewritten in a cell with the number of rewrites exceeding the limitation, or the data is erased (inverted), leading to the end of the lifetime.
Therefore, if rewrites are concentrated on a specific cell, the cell quickly (for example, in about several seconds) reaches the end of lifetime. Thus, the numbers of rewrites in cells are leveled to prevent the concentration of rewrites in a specific cell. The leveling of the numbers of rewrites is generally called wear leveling. The wear leveling is a process of using an address conversion table to dynamically convert a physical address provided from a CPU or the like to a memory system into an internal address for actual writing of data in order to level the numbers of rewrites in the cells.
Here, a simple, new and effective start gap system is known as a system of wear leveling (for example, see the publication of Moinuddin K. Qureshi, Michele Franchescini, Vijayalakshmi Srinivasan, Luis Lastras, Bulent Abali, and John Karidis, “Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling”, IBM Research, [online], [searched Apr. 22, 2014], Internet <URL: http://researcher.watson.ibm.com/researcher/files/us-moinqureshi/papers-sgap.pdf>).
Qureshi, et al. discloses a start-gap system using algebraic mapping between logical addresses and physical addresses, the start-gap system including two registers Start and Gap as well as an additional memory line GapLine for facilitating data migration, Gap tracking the number of lines reshuffled in the memory, Start keeping track of the numbers of reshuffles of all lines in the memory.
Further, an example of a known technique described in a patent application includes a technique of reducing exhaustion of a flash memory (for example, see JP2013-196155A).
JP2013-196155A discloses that when a snapshot condition is met, a management table is saved as a snapshot from a first storage unit to a first block of a second storage unit, a pointer indicating the save location of the management table is saved in a write unit in a second block of the second storage unit, and part of the management table is saved in a non-written area in the write unit of the second block that saves the pointer.
Furthermore, techniques of updating an address conversion table are also known (for example, see JP2007-18499A and WO2012/074554).
JP2007-18499A discloses a storage apparatus including: a 2-chip flash memory that can be accessed in parallel; a page register that acquires data from the flash memory in parallel and that temporarily stores the data; and a control circuit including a RAM provided with an address conversion table for managing contrast between logical addresses and physical addresses on the basis of data stored in parallel in the page register, wherein data is rewritten by update of the address conversion table and addition to a storage medium.
WO2012/074554 discloses restoration of a transaction log including: checking some entries saved in the transaction log to determine a writing pattern based on the entries; reading a memory based on the writing pattern; updating the transaction log with information associated with data read from the memory based on the writing pattern; and updating a logical address (LA) table by using the transaction log.
Further, techniques of duplicating and storing data are also known.
JP7-248978A discloses a non-volatile memory, wherein a first latest write signal is generated and stored after writing of data in a first memory is finished, the same data as the data written in the first memory is written in a second memory, a second latest write signal is generated and stored, a check code indicating whether the latest write signal is normally stored in the memory is generated and stored, and when the check code stored in the memory is determined to be normal, the data is read from the first memory or the second memory according to the latest write signal stored in the memory.
JP10-312338A discloses a memory control apparatus, wherein in address conversion from a virtual address to a physical address, a page table walk process generates two physical addresses of primary and shadow to duplicate data written in a physical memory, and when a failure occurs, the address in which effective data remains is used to enable recovery from the failure.
JP2004-139503A discloses a storage apparatus, wherein the same data is written in a different storage medium when an instruction of minor writing is input, management information of mirror writing (data ID, mirror writing flag, logical address, and the like) is generated, correct data is read from another recording medium if one recording medium is broken when data is read, and at this point, the correct data read from the other recording medium is rewritten in a normal area in place of the data of the broken recording medium.
Further, a technique of causing a plurality of flash EEPROMs to execute write operation at the same time is also known (for example, see Patent Literature 7).
JP7-302176A discloses a semiconductor disk apparatus, wherein a NAND bus interface independently receives sixteen ready/busy signals from the flash EEPROMs to manage the operation state of each flash EEPROM.